This disclosure relates to clock duty cycle sampling that negates the effect of non-ideal sampling circuits or non-ideal sampling clock signals.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.
An electronic device may transmit and receive data between various internal components as well as to other electronic devices based on rising and/or falling edges of clock signals. The circuitry of the electronic device that transmits or receives the data may depend on a relatively stable duty cycle of the clock signal for proper operation. In many cases, for instance, a clock signal may be specified to have a duty cycle of 50%. Since the duty cycle of a clock signal is the ratio of the pulse duration to the pulse period, this means that a clock signal with a 50% duty cycle may be in a HIGH logic state (e.g., 1) for half of the signal period and in a LOW logic state (e.g., 0) for the other half of the signal period. Signals that are in a HIGH logic state for more than half of the signal period have duty cycle above 50%, while signals that are in a LOW logic state for more than half of the signal period have duty cycles below 50%. It should be noted that different circuitry may specify different duty cycles; while a 50% duty cycle may be specified for certain types of circuitry, other duty cycles may be used by other types of circuitry.
Many high-speed circuits use both the rising and the falling edges of the clock signal for timing and may use a clock signal with a 50% duty cycle. Circuits that rely on both clock edges include double-data-rate (DDR) circuitry that includes data circuitry and memory devices, as well as half-rate clock and data recovery (CDR) circuits. If the duty cycle of the clock signal in the circuits is not equal to 50%, the circuits may function improperly owing to timing errors. To maintain a 50% clock duty cycle, duty cycle correction circuits may be used to sample the clock signal to identify the duty cycle and adjust the duty cycle appropriately. Yet the circuits that sample the duty cycle of the clock signals may suffer from process, voltage, and temperature variations that could lead to inaccurate duty cycle measurements and correction.